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| ? integrated circuits group l rs 13 02 st ac ke d chi p 8 m fla sh and 1 m sra m (model no.: lrs13023 ) spec no.: el 11 60 39 issue date: ju ne 11 , 19 99 p roduc t s pecific a tions
sharp lrs13023 l handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2). even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). - office electronics * instrumentation and measuring equipment - machine tools - audiovisual equipment - home appliances * communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-sale operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * control and safety devices for airplanes, trains, automobiles, and other transportation equipment * mainframe computers - traffic control systems * gas leak detectors and automatic cutoff devices - rescue and security equipment * other safety devices and safety equipment,etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. - aerospace equipment - communications equipment for trunk lines - control equipment for the nuclear power industry - medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. l please direct all queries regarding the products covered herein to a sales representative of the company. - sharp lrs13023 2 part 1 overview l.description the lrs1302 is a combination memory organized as 1448,576 x 8 bit flash memory and 131,072x8 bit static ram in one package. it is fabricated using silicon-gate cmos process technology. features oaccess time flashmemoryaccesstime sram access time oopemtingcurrent flash memory read byte write block erase sram operatin% - * * * . . . . . . . . . . . . . . . . - - * * 130 nsmax. 70 nsmax. 12 mamax. (t&ti2oons) 57 r&max. 37 mamax. 25 ma max. hcxjz.=2=) , ostandbycurrent flash memory . . . . 20 @ max. (f-ezf-vc,0.2v, ebo.2v, f-v&o.2v) sk4m . . . . 30 pa max. (s-ezs-vc,0.2v) . . . . 0.7 @ typ. (t,=25?c, s-v,-3v, s-cers-vcc-0.2v) (total standby curnat is the summation of flash memory?s standby current and sram?s one.) opower supply . . . . 2.7v to 3.6v @ead/sram write) 2.7~ to 3.6~ @lash erase/write)(t,=o to 85c osram data retention voltage 2.0 v min. ooperating temperature . . . . 40c to +85?c ofully static operation othree-state output onot designed or rated as radiation hardened 040 pin tsop ( tsop~o-p-0819 plastic package oflash memory has p-type bulk silicon, and srah4 has n-type bulk silicon. the contents described in part 1 take first priority over part 2 and part 3. - sharp lrs13023 2 part 1 overview l.description the lrs1302 is a combination memory organized as 1,048,576x 8 bit flash memory and 131,072x8 bit static ram in one package. it is fabricated using silicon-gate cmos process technology. oaccess time flashmemoryaccesstime sram access time oopemtingcment flash memory read byte write block erase sram operating - * * * . . . . . . . . . . . . . . . . - - * * 130 nsmax. 70 nsmax. 12 mamax. (t&ti2oons> 57 mamax. 37 mamax. 25 mamax. hcxj&oons) , ostandbycurrent flash memory . . . . 20 pa max. (f-ezf-vc,0.2v, ebo.2v, f-v&o.2v) sk4m . . . . 30 @ max. (s-=zs-vc,0.2v) . . . . 0.7 @ typ. (t,=25?c, s-v,-3v, s-cezs-vcc-0.2v) (total standby current is the summation of flash memory?s standby current and sram?s one.) 3power supply . . . . 2.7v to 3.6v @ead/spam write) 2.7~ to 3.6~ (flash erase/write>cr,=o to 85c 3sram data retention voltage 2.0 v min. 3operating temperature . . . . 40c to +85?c ifully static operation 3three-state output jnot designed or rated as radiation hardened 240 pin tsop ( tsop~o-p-0819 plastic package iflash memory has p-type bulk silicon, and sram has n-type bulk silicon. the contents described in part 1 take first priority over part 2 and part 3. m . shari= lrs13023 4 3. notes this product is a stacked tsop package that a 1,048,576x 8 bit flash memory and a 13 1,072 x 8 bit sram are assembled into. power supply and chip enable of flash memory and sram it is forbidden that both f-e and s-e should be low simultaneously. if the two memories are active together, possibly they may not operate normally by interference noises or data collision on i/o bus. both f-v, and s-v, are needed to be applied by the recommended supply voltage at the same time except sram data retention mode. supply power maximum difference (between f-v, and s-v, ) of the voltage is less than -0.3v. sram data retention sram data retention is capable in three ways as below. sram power switching between a system battery and a backup battery needs careful device decoupling from flash memory to prevent sram supply voltage from failing lower han 2.ov by a flash memory peak current caused by transition of flash memory supply voltage or of control si{nals (f-b, f-?% and rp). case i: flash memory is in standby mode. (f-vcc=2.7v to 3.6v) * sram inputs and input/outputs except s-mare needed to be applied with voltages in the range of -0.3v to s-vcc+o.3v or to be open(high-z). * flash memory inputs and input/outputs except f-eand gare needed to be applied with voltages in the range of -0.3v to s-v,,+o.3v or to be open(high-z). case 2: flash memory is in deep power down mode. (f-vcc=2.7v to 3.6v) * sram inputs and input/outputs except s-mare needed to be applied wilh voltages in the range of -0.3v to s-v,c+o.3v or to be open. * flash memory inputs and input/outputs except mare needed to be applied with voltages in the range of -0.3v to s-vc,+o.3v or to be open(high-z). rp is needed to be at the same level as f-v,, or to be open. case 3: flash memory power supply is turned off. (f-vcpov) * fix- low level before turning off flash memory power supply. * sram inputs and input/outputs except s-mare needed to be applied with voltages in the range of -0.3v to s-v,c+o.3v or to be open(high-z). - flash memory inputs and input/outputs except mare needed to be at gnd or to be open(high-z). power up sequence when turning on flash memory power supply, keep i@ low. after f-v,, reaches over 2.7v, keep rp low for more than 1oonsec. device decoupling the power supply is needed to be designed carefully because one of the sram and the flash memory is in standby mode when the other is active. a careful decoupling of power supplies is necessary between sram and flash memory. note peak current caused by transition of control signals. the contents described in part 1 take first priority over part 2 and part 3. sharp lrs13023 5 4.truth table(* 1.3) f-a f-m f-m rp s-a s-m s-m address mode i/o, toi/o, current note llhhhxxx flash read output ec *2,7 lhhhhxxx flash read high-z i,, *4 lhlhhxxx flash write input kc *5,6,7 hxxxllhx sram read output ice hxxxlhhx sr4m read high-z i,, hxxxlxlx sram write input i cc hxxhhxxx standby high-z iss hxxlhxxx deep power down high-z isa *4 notes: * 1. do not make f-c? and s-c8 ?low? level at the samc,limc. * 2. reffcr to dc character&tics. when f-v&v,,.,.,, memory contents can be read, but not altered. * 3. x can be v,,, or v,,, for control pins and addresses, and v,,nx or vi,,,,, for f-v,,,,. see dc characteristics for v,,,k and v,,.,, voltages. * 4. i@ at gnd f0.2v ensures the lowest deep power-down current. * 5. command writes involving block erase, write, or lock-bit configuration are reliably executed when f-v,,=v,, and f-v,@,. block erase, byte write, or lock-bit conliguration with vcc<3.0v or v,,, sharp lrs13023 6 6.absolute maximum ratings notes) * 8.the maximum applicable voltage on any pin with respect to gnd. * 9. except vrp, * 10. except @. * 11. -2.ov undershoot is allowed when the pulse width is less than 20nsec. * 12. +14.ov overshoot is allowed when the pulse width is less than 2onscc. 7.recommended dc operating conditions ct,= -40c to +85?c ) parameter symbol min. typ. max. unit supply voltage vc-2 2.7 3.0 3.6 v input voltage v?, 2.2 v,,+o.3 (*15) v vu. -0.3 (*13: 0.4 v v,,,,(* 14) 11.4 12.6 notes) * 13. -2.ov undershoot is allowed when the pulse width is less than 2onsec. * 14. this voltage is applicable toi@ pin only. * 15. v, is the lower one of s-v, and f-v,,. 8.pin capacitance (t,=25?c, f=lmhz) parameter symbol condition input capacitance gi v,=ov i/o capacitance cia3 v,=ov note) * 16. sampled but not 100% tested min. typ. max. unit 18 pf *16 22 pf *16 the contents described in part 1 take first priority over part 2 and part 3. sharp lrs13023 8 part2 flash memory contents page page .. introduction ........................................................... 9 1.1 new features.. ........................................................... -9 1.2 product overview ...................................................... 9 4.10 clear block lock-bits command.. ....................... 20 !. principles of operation ................................... 12 2.1 data protection ......................................................... 12 i.bus operation.. ........................................... . ............ 13 3.1 read ........................................................................... 13 3.2 output disable ........................................ ;............... 13 3.3 standby ...................................................................... 13 3.4 deep power-down ................................................... 13 3.5 read identifier codes operation ........................... 14 3.6 write ........................................................................... 14 5. design considerations .................................... 28 5.1 three-line output control .................................... 28 5.2 power supply decoupling.. .................................... 28 5.3 v,, trace on printed circuit boards.. ................... 28 5.4 v,,, v,,, i?is transitions.. ...................................... 29 5.5 power-up/down protection.. ................................ 29 5.6 power dissipation.. .................................................. 29 i. command definitions ....................................... 14 4.1 read array command ............................................ 17 4.2 read identifier codes command ......................... .17 4.3 read status register command.. .......................... .17 4.4 clear status register command ........................... .17 4.5 block erase command ............................................ 17 4.6 byte write command .............................................. 18 4.7 block erase suspend command ........................... .18 4.8 byte write suspend command.. ........................... .19 4.9 set block and master lock-bit commands ......... -19 6.electrical specifications ............................... 30 6 1 absolute maximum ratings.. ................................. 30 6.2 operating conditions.. ............................................ 30 6.2.1 ac input/output test conditions.. ................ 31 6.2.2 dc characteristics ............................................. 32 6.2.3 ac characteristics - read-only operations ... 34 6.2.4 ac characteristics - write operations.. ......... .36 6.2.5 alternative a-controlled writes ................... 38 6.2.6 reset operations ................................................ 40 6.2.7 block erase, byte write and lock-bit configuration performance.. ........................... 41 sharp lrs13023 8 part2 flash memory contents page page .. introduction ........................................................... 9 1.1 new features.. ........................................................... -9 1.2 product overview ...................................................... 9 4.10 clear block lock-bits command.. ....................... 20 !. principles of operation ................................... 12 2.1 data protection ......................................................... 12 i.bus operation.. ........................................... . ............ 13 3.1 read ........................................................................... 13 3.2 output disable ........................................ ;............... 13 3.3 standby ...................................................................... 13 3.4 deep power-down ................................................... 13 3.5 read identifier codes operation ........................... 14 3.6 write ........................................................................... 14 5. design considerations .................................... 28 5.1 three-line output control .................................... 28 5.2 power supply decoupling.. .................................... 28 5.3 v,, trace on printed circuit boards.. ................... 28 5.4 v,,, v,,, i?is transitions.. ...................................... 29 5.5 power-up/down protection.. ................................ 29 5.6 power dissipation.. .................................................. 29 i. command definitions ....................................... 14 4.1 read array command ............................................ 17 4.2 read identifier codes command ......................... .17 4.3 read status register command.. .......................... .17 4.4 clear status register command ........................... .17 4.5 block erase command ............................................ 17 4.6 byte write command .............................................. 18 4.7 block erase suspend command ........................... .18 4.8 byte write suspend command.. ........................... .19 4.9 set block and master lock-bit commands ......... -19 6.electrical specifications ............................... 30 6 1 absolute maximum ratings.. ................................. 30 6.2 operating conditions.. ............................................ 30 6.2.1 ac input/output test conditions.. ................ 31 6.2.2 dc characteristics ............................................. 32 6.2.3 ac characteristics - read-only operations ... 34 6.2.4 ac characteristics - write operations.. ......... .36 6.2.5 alternative a-controlled writes ................... 38 6.2.6 reset operations ................................................ 40 6.2.7 block erase, byte write and lock-bit configuration performance.. ........................... 41 sharp lrs13023 9 introduction his datasheet contains lrs1302 specifications. iection 1 provides a flash memory overview. sections !, 3,4, and 5 describe the memory organization and unctiordity. section 6 covers electrical specifications. ..l new features the lrs1302 smartvoltage flash memory maintains )ackwards-compatibility with sharp?s 28f008sa. cey enhancements over the 28f008sa include: smartvoltage technology *enhanced suspend capabilities jn-system block locking 30th devices share a compatible, status register, and oftware command set. these similarities enable a clean upgrade from the 28foo8sa to lrs1302. when upgrading, it is important to note the following iifferences: -because of new feature support, the two devices have different device codes. this allows for software optimization. .vpplk has been lowered from 6sv to 1.5v to support 2.7v-3.6v block erase, byte write, and lock-bit configuration operations. designs that switch vpp off during read operations should make sure that the vp, voltage transitions to gnd. *to take advantage of smartvoltage technology, allow vp, connection to 2.7v-3.6v. i.2 product overview the lrs1302 is a high-performance &mbit ;martvoltage flash memory organized as 1 mbyte of 8 >its. the 1 mbyte of data is arranged in sixteen &kbyte blocks which are individually erasable, o&able, and unlockable in-system. the memory map s shown in figure 2. smartvoltage technology provides a choice of vcc and vp, combinations, as shown in table 1, to meet system performance and power expectations. v, at 2.7v to 3.6v eliminates the need for a separate 12v converter. in addition to flexible erase and program voltages, the dedicated vpp pm gives complete data protection when vp, i vp,,. table 1. v,, and vp, voltage combinations offered by smartvoltage technology ;_. vcc voltage vpp voltage 2,7v to 3.6v(?l) 2.7v to 3.6v i note? ? ?1. flash erase/write(t*=o?c to 85c) internal vcc and vw detection circuitry automatically configures the device for optimized read and write operations. a command user interface (cut) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cut initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. a block erase operation erases one of the device?s 64kbyte blocks typically within 1.8 second independent of other blocks. each block can be independently erased 100,000 times (1.6 million block erases per device). block erase suspend mode allows system software to suspend block erase to read or write data from any other block. writing memory data is performed in byte increments typically within 17 us. byte write suspend mode enables the system to read data or execute code from any other flash memory array location. 1 sharp lrs13023 10 ~individual block locking uses a combination of bits, ?sixteen block lock-bits and a master lock-bit, to lock land unlock blocks. block lock-bits gate block erase and ?byte write operations, while the master lock-bit gates ~block lock-bit modification. lock-bit configuration loperations (set block lock-bit, set master lock-bit, and clear block lock-bits commands) set and cleared lock-bits. the status register indicates when the wsm?s block erase, byte write, or lock-bit configuration operation is finished. the access time is 130 ns (tavqv) over the commercial temperature range (-40c to +bs?c) and v,, supply voltage range of 2.7v-3.6v. the automatic power savings (ai%) feature substantially reduces active current when the device is in static mode (addresses not switching). when a and rf pins are at v,,, the i,, cmos standby mode is enabled. when the rp pin is at gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (tphqv) is required from rp switching high until outputs are valid. likewise, the device has a wake time (tphel) from m-high until writes to the cui are recognized. with rp at gnd, the wsm is reset and the status register is cleared. 4 x : 16 occcdc.r . 64kbyle . blocb figure 1. block diagram sharp lrs13023 11 svm f40-419 i/o&o~ - ce rp oe _. _- we bp vcc gnd rote: v,-, type input input/ output input input input input supply supply ground: do not float any ground pins. ,p, n, m and we mean f-v,,, f-v,,, f-a, fa and f-we. supply table 2. pin descriptions name and function address inputs: inputs for addresses during read and write operations. addresses are internally latched during a write cycle. data input/outputs: inputs data and commands during cui write cycles; outputs data during memory array, status register, and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. chip enable: activates the device?s control logic, input buffers, decoders, and sense amplifiers. a-high deselects the device and reduces power consumption to standby levels. reset/deep power-down: puts the device in deep power-down mode and resets internal automation. m-high enables normal operation. when driven low, p inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. ris at v,, enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is - set. rp=v,,, overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. block erase, byte write, or lock-bit configuration with v,, shari= lrs13023 13 when vppivpplk, memory contents cannot be altered. the cui, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to vp+. all write functions are disabled when v,, is below the write lockout voltage vlko or when rp is at vl,. the device?s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations. 3 bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory :onform to standard microprocessor bus cycles. 3.1 read .c information can be read from any block, identifier :odes, or status register independent of the vp, voltage. rp can be at either vl, or v,,. the first task is to write the appropriate read mode :ommand (read array, read identifier codes, or read status register) to the cui. upon initial device tower-up or after exit from deep power-down mode, :he device automatically resets to read array mode. four control pins dictate the data flow in and out of --- :he component: ce, oe, we, and m. ce and m must >e driven active to obtain data at the outputs. m is the device selection control, and when active enables the ielected memory device. m is the data output i/o&o,) control and when active drives the ielected memory data onto the i/o bus. we must be it vi, and m must be at v,, or v,,. figure 12 llustrates a read cycle. 1.2 output disable mith 0ly at a logic-high level (vt,), the device outputs ire disabled. output pins i/0,-1/0, are placed in a high-impedance state. 3.3 standby n at a logic-high level (v,,) places the device in standby mode which substantially reduces device power consumption. i/o&o, outputs are placed in a high-impedance state independent of oe. if deselected during block erase, byte write, or lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. 3.4 deep power-down i?ij at v,, initiates the deep power-down mode. in read modes, m-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. rp must be held low for a minimum of 100 ns. time tphqv is required after return from power-down until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase, byte write, or lock-bit configuration modes, m-low will abort the operation. memory contents being altered are no longer valid; the data may be partially erased or written. time tphwl is required after rp goes to logic-high (vi,) before another command can be written. as with any automated device, it is important to assert rp during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp?s flash memories allow proper cpu initialization following a system reset through the use of the i?l? input. in this application, rp is controlled by the same m signal that resets the system cpu. sharp lrs13023 14 1.5 read identifier codes operation 3.6 write the read identifier codes operation outputs the nanufacturer code, device code, block lock :onfiguration codes for each block, and the master ock configuration code (see figure 3). using the nanufacturer and device codes, the system cpu can u,rtomatically match the device with its proper algorithms. the block lock and master lock :onfiguration codes identify locked and unlocked ~1ock.s and master lock-bit setting. writing commands to the cui enable reading of device data and identifier codes. they also control inspection and clearing of the status register. when v,--=vccl and vpp=vpph, the cui additionally controls block erasure, byte write, and lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the byte write command requires the command and address of the location to be written. set master and block lock-bit commands require the command and address within the device (master lock) or block within the device (block lock) to be locked. the clear block lock-bits co mmand requires the command and address within the device. foo04 fooo3 reserved for future implementation foooz 1 block 15 lock configuration code foool foooo iffff looo4 1ooo3 reserved for future implementation block 1 (blocks 2 through 14) ? reserved for future implementation i block 1 lock configuration code offff oooo4 reserved for future implementation oooo3 master lock configuration code ------------------------------------. moo2 block 0 lock configuration code ~~~~~~~~----__-__---________________( ooml device code --------_-__________----------------. manufacturer code block the cui does not occupy an addressable memory location. it is written when we and a are active. the address and data needed to execute a command-are latched on the rising edge of we or ce (whichever goes high first& stand,ard microprocessor write timings are used. jqures:13 and 14 illustrate we and m-controlled write operahons. : 4 command d&initlon~ when the vp, voftage i vpplk, read operations from the status register, identifier codes, or blocks are enabled. placing vp,, on.vpp enables successful block erase, byte write and lock-bit configuration operations. device operations are selected by writing specific commands into the cui. table 4 defines these commands. figure 3. device identifier code memory map sharp lrs13023 15 notes: 1. refer to dc characteristics. when vppivpp,, memory contents can be read, but not altered. 2. x can be vi, or v,, for control pins and addresses, and vp,, or vp,, for vp,. see dc characteristics for vw, and v,,, voltages. 3. i@ at gnd&.2v ensures the lowest deep power-down current. 4. see section 4.2 for read identifier code data. 5. command writes involving block erase, write, or lock-bit configuration are reliably executed when vpp=vpph and vcc=vcciu~=o to 85 ?c) . block erase, byte write, or lock-bit configuration with v, sharp lrs13023 17 :.l read array command jpon initial device power-up and after exit from deep jowerdown mode, the device defaults to read array node. this operation is also initiated by writing the lead array command. the device remains enabled for eads until another command is written. once the nternal wsm has started a block erase, byte write or sck-bit configuration, the device will not recognize he read array command until the wsm completes its lperation unless the wsm is suspended via an erase luspend or byte write suspend command. the read bray command functions independently of the vp, poltage and m can be v,, or v,,. ,.2 read identifier codes command ?he identifier code operation is initiated by writing the lead identifier codes command. following the ommand write, read cycles from addresses shown in ?igure 3 retrieve the manufacturer, device, block lock onfigura tion and master lock configuration codes (see ?able 5 for identifier code values). to terminate the nperation, write another valid command. like the lead array command, the read identifier codes ommand functions independently of the vp, voltage - nd rp can be v,, or v,,. following the read dentifier codes command, the following information an be read: table 5. identifier codes block lock configuration .block is unlocked *block is locked -reserved for future use master lock configuration sdevice is unlocked ,device is locked ,reserved for future use iote: . x selects the specific block lock configuration code to be read. see figure?3 for the device identifier code memory map. . 4.3 read status register command the status register may be read to determine when a block erase, byte write, or, lock-bit configuration is complete and whether the operation completed successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe or ce, whichever occurs. oe or iz must toggle to v,, before further reads to update the status register latch. the read status register command functions independently of the vp, voltage. rp can be v,, or v,,. 4.4 clear status register command status register bits sr.5, sr.4, sr.3, and sr.1 are set to ?1?s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 7). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. the status register may be polled to determine if an error occurre during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied vp, voltage. rp can be v,, or v,,. this command is not functional during block erase or byte write suspend modes. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 4). the cpu can detect block erase completion by analyzing status register bit sr.7. sharp lrs13023 18 when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the clji remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to ?1?. also, reliable block erasure can only occur when vcc=vcci and v,=v,,,. in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while vppflppm, sr.3 and sr5 will be set to ?1?. successful block erase requires that the corresponding block lock-bit be cleared or, if set, that m=v,. if block erase is attempted when the corresponding block lock-bit is set and m=v,,, sr.1 and sr5 wi.li be set to ?1?. block erase operations with v, sharp lrs13023 22 suspmd black check if deeired full status check procedure comment3 read i status register data i check sr7 l.w!sm ready o=wsm busy repeat for subsequent block erasores. full ,tailhls check can be done after each block erase or after a eequence of bbck erasuree. write ffh after ibe kut operation to phwe device in read array mode. read status beg&r ihtacsee above) block emsesucceseful comments cheek sr3 l=vpp error detect check sri idkvice protect detect i?&vt,,block lock-bit is set only required for systems implementing lock-bit configuration i check sr4.5 stmdby both i=command sequence error check srs l=block erase error srs,sr4sr3 and sr.1 are only cleared by the clear status register command in casea where multiple blocks are erased before full etatoe b checked. if error isdetected, clear the status register before attempting retry or other error recovery. figure 4. automated block erase flowchart shari= lrs13023 write 4oh or 10h add- wrih byte data and addrerr fullztatijs check procedure datagee above) device protect error bus opation command comment3 write byte write data=data to be written addr=locamon to be writbn i rnd i status register data i repeat for subsequent byte writes.. sr full stahn check can be done after each byte write. or after a sequence of byte write. write ffh after the last byte write operation to place device in read array mate. bus opdi0n command comments 1 standby 1 check sr3 l=vpp error detect standby check srl 1=cevice protect detect !@=v~~,block lock-bit is set only required for systems implementing lock-bit configuration standby check sr4 l--data wrtte ermr sr45rs3 and sri are only cleared by the clear stahm register command in cases when multiple locations are written before if enur is detected, clear the status register before attempting figure 5. automated byte write flowchart :. .:.,.&?arp .:? lrs13023 24 w su.7.a 0 i checksr7 1dvsmrcpdy o=wsm busy i wrik i emm dala=doh resume i addrrx i figure 6. block erase suspend/resume flowchart wrib? byte write &pd dah=boh addrx i - i i sbhw rrgister dab add-x * i wrik i -amy i mta=ffh addr=x rd red amy locatiom othrr than that being wrhn. figure 7. byte write suspend/resume flowchart . sharp ? . .,,,i - lrs13023 block/devke addraa writeolhfth. block/device add= check if desired fullstatljscheckproceujre set luck-bit emw i set dz?tp=6ljh bkck/mrsta addmbbxk addrrsj(blaw, lack-bit setup dcvia address&laster) &pent for subsquent lack-bit aetoperattom. pull ,btus check an be don after ench kxk-blt set operation / or after p aqucm of lock-bit set opemtlons. write ith after the last lock-bit set opentlan io pl.m de+ in read array made. i check sr3 ld?pp error detect checksrl i=oevh protect detect b-v,, (set master lack-bit onentton) i%v,?, master lock-bit is set (set block lack-bit operation) ciwck~45 both l-command scquencs emx i check sr4 l&t lack-bit error sr55r4,sr3andsrlareoniyclearedbythe aedtahra command in cases where multiple lack-bib am set before- if aror is detected, dear the stahu register befoe attempting figure 8. set block and master lock-bit flowchart 26 lrs13023 27 write 60h si wrttc wh sbtua rlghbr 3 0 sr.7. 1 full status check procedure aear bbck dh=wh luck-bib confirm add-x write ffh after tk clear block lock-bib opwatton to ptw devke in mad array mode. commcnb ckk 547.1 l=ddce protect detect i&v,?, master lsck-bit is set check sr4.5 both i=commad sequmctermr i cbecksr5 l=clear blak lack-bib !&or i i sr.s5r4sr3andsr.1arem?tyciearcdbythe acershhu regbbrcommand. figure 9. clear block lock-bits flowchart sharp _____ lrs13023 5 design considerations i.1 three-line output control the device will often be used in large memory arrays. sharpprovides three control inputs to accommodate nultiple memory connections. three-line control xovides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention wili not occur. to use these control inputs efficiently, an address iecoder should enable m while m should be :onnected to all memory devices and the system?s read control line. this assures that only selected nemory devices have active outputs while deselected nemory devices are in standby mode. y should be :onnected to the system powergood signal to prevent unintended writes during system power ran&ions. powergood should also toggle during system reset. i.2 power supply decoupling ?ash memory power switching characteristics require :areful device decoupling. system designers are nterested in three supply current issues; standby urrent levels, active current levels and transient peaks rroduced by falling and rising edges of m and m. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device shouid have a 0.1 uf ceramic capacitor connected between its v,, and gnd and between its v,, and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7 pf electrolytic capacitor should be placed at the array?s power supply connection between vc- and gnd. the bulk capacitor will overcome voltage slumps caused by pc board &ace inductance. 5.3 v,, trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the v,, power supply trace. the v,, pin supplies the memory cell current for byte writing and block erasing. use similar trace widths and layout considerations given to the v,, power bus. adequate v, supply traces and decoupling will decrease v,, voltage spikes and overshoots. lrs13023 29 5.4 v,,, v,,, i?is transitions 3lock erase, byte write and lock-bit configuration are lot guaranteed if vpp fails outside of a valid vp= ange, v, falls outside of a valid vccl range, or rp n,, or v,,. if v,, error is detected, status register )it sr3 is set to ?1? along with sr4 or sr5, depending m the attempted operation. if rp transitions to v, luring block erase, byte write, or lock-bit :onfiguration, the operation will abort and the device ti enter deep power-down. the aborted operation nay leave data partially altered. therefore, the :ommand sequence must be repeated after normal operation is restored. device power-off or d ransitions to v,, clear the status register. the gui latches co mmands issued by system software md is not altered by v, or a transitions or wsm ~tions. its state is read array mode upon power-up, ifter exit from deep power-down or after vcc ransitions below vu0 after block erase, byte write, or lock-bit configuration, ?ven after v,, transitions down to v,,,, the gui nust be placed in read array mode via the read array :ommand if subsequent access to the memory array is iesired. 5.5 power-up/down protection the device is designed to offer protection against t&dental block erasure, byte writing, or lock-bit :onfiguration during power transitions. upon >ower-up, the device is indifferent as to which power upply (v,, or v,,) powers-up first. internal circuitry ?esets the gui to read array mode at power-up. a system designer must guard against spurious writes for v,eoltages above vu0 when v,, is activ;.:; both we and m must be low for a comman * , driving either to vih will inhibit writes. the gui?s two-step command sequence architecture provides added level of protection against data alteration. in-system block lock and unlock capability prevents inadvertent data alteration. the device is disabled while m=v,, regardless of its contro1 inputs state. 5.6 power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memory?s nonvolatility increases usable battery life because data is retained when system power is removed. in addition, deep powerdown mode ensures extremely low power consumption even when system power is applied.. for example, portable computing products and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by. lowering i?p to :vk standby or sleep,modes. if access is again needed, the devices can be read following the tphqv and tphwl wake-up cycles required after rp isfirst raised to v,,. see ac characteristics- read only and write operations and figures 12,13 .and 14 for more information. electrical specifications .1 absolute maximum ratings* :ommercial operating temperature during read, block erase, byte write and lock-bit configuration . . . . . . . . . -40c to +85@) temperature under bias . . . . . . . . . . . . . . . . . . -40c to +85?c torage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125?c toltage on any pin (except vcc, vp,, and m> . . . . . . . . . . . . -2.ov to +7.0vt2) rc- supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.ov to +7.0vt2) tpp update voltage during block erase, byte write and lock-bit configuration . . . . . . . . . . . . . . -2.ov to +14.ov(23) r voltage with respect to gnd during lock-bit configuration operations . . . . . . . . . -2,ov to +14.0v(2j) output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . . . looma(4) *warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. s 4 notes: 1. operating temperature is for commercial product defined by this specification. t 2. all specified voltages are with respect to gnd. minimum dc voltage is -0sv on input/output pins and -0.2v on vc- and v, pins. during transitions, this level may undershoot to -2.ov for periods ~2011s. maximum dc voltage on input/output pins and v,, is v,,+o.5v which, during transitions, may overshoot to v,, +2.ov for periods <2ons. 3. maximum dc voltage on vp, and rp may overshoot to +14.ov for periods c2ons. 4. output shorted for no more than one second. no more than one output shorted at a time. c 6 .2 operating conditions temperature and v,, operating conditions symbol parameter notes min max unit test condition t* operating temperature -40 +85 ?c ambient temperature v,,, v,, supply voltage (2.7v-3.6v) 1 2.7 3.6 v jote: . flash erase/write (ta=o to 85c) shari= lrs13023 30 shari= lrs13023 31 .2.1 ac input/output test conditions ~~~z2~~~~ ac test inputs are driven at 2.7v for a logic?l? and o.ov for a logic ?0.? input timing begins, and output timing ends, at 1.35v. input rise and fall times (10% to 90%) cl0 ns. figure 10. transient inputjoutput reference waveform for v,-=2.7v-3.6v 13 ln914 -c cl includes jig capacitance figure 11. transient equivalent testing load circuit test configuration capacitance loading value test configuration c, ,(pf) vo=2.7v-3.6v so sharp lrs13023 32 i.2.2 dc char4cteristics dc characteristics vcc=2.7v-3.6v test spl parameter notes typ max unit conditions il1 input load current 1 20.5 pa vcc=vccmax v,,,,=vtc or gnd il0 output leakage current 1 20.5 pa vcc=vccmax vnr tt=vcc or gnd kcs v,, standby current 1,5 20 100 pa cmos inputs kc=v,,max ce=rf=vc-c-~0.2v 0.2 2 ma ttl inputs vcc=vc-max ceaev,~ kcd v,, deep power-down 1 20 pa i@=gnd+-0.2v current i,, ,t=oma kcr v,-- read current 1,45 7 12 ma cmos inputs vcc=vccmax, ~=gnd c f=5mhz(3.3v, 2.7v)101 ,=oma 8 18 ma -i-rl inputs - vcc=vccmax, ce=gnd f=5mhz(3.3v, 2.7v)i,, ,=oma kcw v,, byte write orset l6 17 ma vpp=vlth lock-bit current kce v,, block erase or clear 1,6 17 ma vpp=vlth block lock-bits current kcws v,- byte write or block 12 1 6 ma a=&, i(-(.fs erase suspend current bps vp, standby or read 1 22 215 pa v,,iv~~ ipp* current 10 200 pa v,p>v(-r iltd vpp deep power-down 1 0.1 5 pa m=gnd+0.2v current 4tw vp, byte write or l6 40 ma vlt=vpph setlock-bit current ippe vp, block erase orclear l6 20 ma vpp=vpph lock-bit current ippws vp, byte write or block 1 10 200 @ vpp=vpph ppfs erase suspend current shari= lrs13023 33 dc characteristics (continued) voh2 output high voltage cmos) vp,, v,, lockout during normal operations v,, vp, during byte write, block erase or lock-bit operations v, .ko v,, lockout voltage vi-ii-i rp unlock voltage notes: 6 3,6 7,; 0.85 v,, vcc -0.4 2.7 2.0 11.4 1.5 3.6 12.6 v v,-=v,,min &=-2.5ua v v v ta=o to 85c v v set master lock-bit override master and block lock-bit 1. all currents are in rms unless otherwise noted. 2. kcws~dhes are specified with the device de-selected. if read or byte written while in erase suspend mode, the device?s current draw is the sum of kms or kces and &-- or &--jj, respectively. 3. block erases, byte writes, and lock-bit configurations are inhibited when vppivppx, and not guaranteed in the range between vppx(max> and vp&&n) and above vp&max). 4. automatic power savings @f?s) reduces typical ~c-j to 3ma at 3.3v v,- in static operation. 5. cmos inputs are either v,-c- +0.2v or gndk0.2v. ttl inputs are either v, or v,. . . 6. sampled, not 100% tested. 7. master lock-bit set operations are inhibited when d=v,,. block lock-bit configuration operations are inhibited when the master lock-bit is set and rp=v,. block erases and byte writes are inhibited when the corresponding block-lock bit is set and p=vih. 8. m connection to a v, supp 1 y is allowed for a maximum cumulative period of 80 hours. shari= lrs13023 34 6.2.3 ac characteristics - read-only operations(?) vo=2.7v-3.6v, ta=-400c to +8s?c sym 1 parameter 1 notes 1 min i max 1 unit ] ta?*v 1 read cycle time 130 ! ! ns 1 rddress to output delay ! i ! 130 ! ns 1 rt delay rr hieh to outout delav 2 i 130 ns 600 ix.3 i bh )i2 to output delay i, - it in low 2 atput in high 2 1tinlowz 2 ii0 ns 3 0 ns 3 55 ns 3 0 ns ce to outp 1 a high to 7 / oe to outo; cm-ii] gh to ( output in high z 3 20 ns output hold from address, a or oe change, 3 0 ns whichever occurs first notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. m may be delayed up to telqv-klqv 3. sampled, not 100% tested. affer the falling edge of a without impact on telqv. shari= lrs13023 .ddress~a) device address selection data valid , ----------- address stable , -__----__-_ tavel- high z c 4 valid output ::::::::::y:::y%{ high z vol i, tavnv vcc -----------7 4 tphov c vih i -e(p) vil ------------ figure 12. ac waveform for read operations sharp lrs13023 ac characteristics - write operation(?) vo=27v-3.6v, t,=o?c to +85?c parameter notes min max unit rime 130 ns write cycle * rp high recovery to we going low a setup to we going lqw 2 i 1 p 10 ns width -- ld to m goi ng high ing high 50 ns 2 100 ns -1 2 100 ns i 3 50 ns 1 notes: 1. read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-onry operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 4 for valid a, and b for block erase, byte write, or lock-bit cm@.uation. .. 4. v, should be held at v,,, ( and if necessary trf should be held at v,) untilidetermination.of block erase, byte write, or lock-bit configuration success (sr1/3/4/5=0). sharp lrs13023 37 addresses(a) b(e) m(g) datawo) 1 2 3 4 5 6 ------ vih vil i vih c4vav tvwh vil i hhcl vih vil vih vil vih vil vi ill vii i i i vppw notes: 1. vcc power-up and standby. 2. write block erase or byte write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. figure 13. ac waveform for t&%controlled write operations sharp lrs13023 38 6.2.5 alternative m-controlled writes(?) v -27v-3.6v. ta =o?c pp- to +85?c notes: 1. in systems where n defines the write pulse width (within a longer we tir&tg waveform), all setup, hold, and inactive we times should be measured relative to the a waveform. 2. sampled, not 100% tested. 3. refer to table 4 for valid ain and din for block erase, byte write, or lock-bit configuration. 4. vp, should be held at vp,, ( and if necessary m should be held at v m) un$l determination,of block erase, byte write, or lock-bit configuration success (sr1/3/4/5=0). sharp lrs13023 39 1 2 3 4 5 6 ----- -? vih addresses(a) vil me) data(i/o) vih vil vih vil vii-i vil vih vi, vhh rf(p) viii i i \ notes: 1. vcc power-up and standby. 2. write block erase or byte write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. figure 14. alternate ac waveform for ce-controlled write operations sharp lrs13023 40 i.2.6 reset operations fp(p, vih vil blph (alreset during read array mode, block erase, byte write or lock-bit configuration 27v vcc t vil i - tvph - izp(p) vih i vil 7- c (b)f? rising timing figure 15. ac waveform for reset operation reset ac specifications vcr=2.7-3.6v sjvii parameter notes min max unit :plph rp pulse low time 100 ns (if w is tied to vcc, this specification is not applicable) yph v,, 2.7v to rp high 1 100 ns lotes: . when the device power-up, holding -iss low minimum 1oons is required after v,, has been in predefined range and also has been in stable there. ?sharp lrs13023 41 i 6.2.7 block erase, byte wrlte and lock-bit configuration pewormance(3) notes: 1. typical values measured at ta- -+2s?c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. sampled but not 100% tested. sharp lrs13023 42 part3sram contents 1. description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2. truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5. recommended dc operatiig conditions .......................................................... 6. dc electrical characteristics .............................................................................. 7. ac electrical characteristics ............................................................................. 46 8. data retention characteristics ......................................................................... 47 9. timing chart ..................................................................................................... 48 sharp lrs13023 43 1 .description the lrs 1302 is a static ram organized as 13 1,072 x 8 low-power standby mode. it is fabricated using silicon-gate cmos process technology. features access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data retention current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..s...... single power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . l fully static operation three-state output not designed or mted as tadiation hardened n-type bulk silicon bit which provides 70 ns(m=) 25 ma(max. ~a~200ns) 30 @(max.) 0.7 pa(typ. v,,=3v, t,=25?c) 2.7v to 3.6v -40c lo +85?c sharp lrs13023 44 2.trut.h table (ce, oe and %% mean s-b, s-zand s-a respectively.) (x=don?t care, l.=low, h=high) 3.block diagram (v, means s-v,-j k-- row memory -y (512x2048) 1 circuit r? column decolde$ y 8 control shari= lrs13023 4.absolute maximum ratings parameter symbol ratings supply voltage vcc -0.2 to +4.6 input voltage(* 1) yn -0.3 (*2) to v&o.3 operating temperature ? topr -4) to +i35 storage temperature t *l -65 to +125 notes * 1. the maximum applicable voltage on any pin with respect to gnd. * 2. -2.ov undershoot is allowed to the pulse width less than 5ons. unit v v ?c ?c krecommended dc operating conditions parameter syrhbol min. typ. supply voltage v w 2.7 3.0 input voltage vii, 2.2 vu. -0.3 (*3) note * 3. -2.ov undershoot is allowed to the pulse width less than 50ns. (t,= -40c to +85?c > max. unit 3.6 v v,,+o. 3 v 0.4 v 6.dc electrical characteristics parameter symbol conditions (t,= -40c to +85?c , v,--= 2.7v to 3.6v ) min. typ. max. unit input leakage hj v,=ov to v, -1.0 1.0 current ia output ki3 ce=v, or leakage oe=v, or%%!, -1.0 1.0 pa current v,=ov to v, operating ec1 ce=v, ,v,,=v, or v,,, &dmin supply i,=oma 3o ma current kc2 i%10.2v bax=200ns v,=o.2v or v,-0.2v b=oma 25 ma standby *se ce r v,-0.2v 0.7 30 current (*4) cra , i sal ce=v, **? ma output v, h=2.oma 0.4 v voltage v ai , i,,=2.oma 2.4 v note $4. t,=25?c, ve3.ov shari= lrs13023. 46 7. ac electrical characteristics ac test conditions input pulse level 0.4v to 2.4v input rise and fall time 5ns 1 input and output timing ref. level i 1.5v i i output load 1m+cl~1oopf) (*5) note * 5. including scope and jig capacitance. read cvcie ct,= 40c to +85?c 9 vcc= 2.7v to 3.6v > 70 i ns i 70 i ns i 40 i ns i i i ns write cycle (?i+,= 4c to +85?c , vcc= 2.7v to 3.6v > *6 *6 *h note * 6. active output to high impedance and high impedance to output active tests specified for a f2oomv transition from steady state levels into the test load. sharp lrs13023 47 8.data retention characteristics parameter data retention supply voltage data retention supply current chip enable setup time chip enable hold time cl= -40c to +85?c ) symbol conditions min. typ. max. unit - v c(dr ce _2 vc,p,-0.2v 2.0 3.6 v gn]r v-=3v 1 t,=25?c 0.7 1.0 w - ce zvndr-0.2v 25 cla kdr 0 ms tr 5 ms -c sharp lrs13023 48 9.timing chart read cycle timing chart (*7) < kc > oe i i t-l 43, note * 7. % is high for read cycle. write cycle timing chart (?% controlled) oe ce 77 < tw > i( \( \\\\ / t \&i-> 1111 aw ttw (*g) (*11) \ \ td*8) ;&,t > 7 sharp lrs13023 49 write cycle timing chart (m low fixed) ce din notes < l4 +4n> i (*la / data valid \ - - * 8. a write occurs during the overlap of a low ce! and low we. a write begins at the latest transition among= going low and we going low. a write ends at the earliest transition among= going high and we going high. t,, is measured from the beginning of write to the end of write. * 9. &,, is measured from the- going low to the end of write. * 10. t,,, is measured from the address valid to the beginning of write. * i 1. t,, is measured from the end of write to the address change. twr a pp lies in case a write ends at?% or we going high. * 12. during this period, i/o pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. * 13. if ce goes low simultaneously with wl? going low or after we going low, the outputs remain in high impedance state. * 14. if ce goes high simultaneously with we going high or before we going high, the outputs remain in high impedance state. -_ sharp lrs13023 shari= lrs13023 51 part4 package and nackinn specification 1 1. package outline specification refer to drawing no.aa2 0 17 2. markings 2 - 1. marking contents ( 1) product name : l r s 1 3 0 2 (2) company name : sharp ( 3 > date code (example) y y indicates the product was manufactured in the wwth week of 19yy. l-3) - denotes the production ref.code( denotes the production week. (lower two digits of the year.) (4) the marking of ?japan? indicates the country of origin. 2-2. marking layout refer drawing no.aa 2 0 1 7 (this layout does not define the dimensions of marking character and marking position.) 3. surface mount conditions please perform the following conditions when mounting ics not to deteriorate ic quality. 3-l .soldering conditions(the following conditions are valid only for one time soldering.) mounting method temperature and duration measurement point reflow soldering peak temperature of 230c or less, ic package (air) duration of less than 15 seconds. 200c or surface over,duration of less than 40 seconds. temperature increase rate of l-4?c/second ________________________________________-------------------------------------------------------------------------------------------------------- manual soldering 260c or less, duration of less ic outer lead (soldering iron) than 10 seconds surface 3-2. conditions for removal of residual flux (1) ultrasonic washing power : 25 watts/liter or less (2) washing time : total 1 minute maximum (3) solvent temperature : 15-40c shari= lrs13023 52 4. packing specification (embossed carrier taping specification) this standard apply to the embossed carrier taping specificat ion for ics to be delivered from sharp corporation. sharp?s embossed carrier taping specification are generally based on those set forth by the japanese industrial standard jis c 0806 and the eia481a. 4 - 1. tape structure . embossed carrier tape is made of conductive plastic. the embossed portions of the carrier tape are filled with ic packages and covered with a top covering tape to enclose them. 4-2. taping reel and embossed carrier tape size *for the taping reel and embossed carrier tape sizes, refer to the attached drawings (no.cv674 and cv755) 4-3. ic package enclosure in embossed carrier tape *the ic package enclosure direction in the embossed portion as it compares to the direction in which the tape is pulled is indicated by an index mark on package (index mark indicate the no.1 pin on package) in the attached drawing (no. cv522). 4 -4. missing ic packages inside embossed carrier tape *the number of missing ic packages inside the embossed carrier tape should not exceed 0.1% of the total enclosed in the tape per reel, or 1, whichever may be larger.there should never be more than two consecutive missing ic package. 4 - 5. tape joints -the embossed carrier tape should not have more than one joint per reel. 4-6. peeling strength of the top covering tape *peeling strength must meet the following conditions. 1) peeling angle at 165? to 180? 2) peeling speed at 300mm/min. 3) peeling strength at 0.2 to 0.7n(zo to 70gf) dhaiinc dlhectio# [emhosed carrim rape lrs13023 53 4 - 7. packing . the top covering tape (leader side) at the leading edge of the embossed carrier tape, and the trailing edge of the embossed carrier tape, shall be held in place with paper adhesive tape exceeding 3omm in length. . the leading and trailing edges of the embossed carrier tape shall be left empty (with embossed portions not filled with ic packages), in the attached drawing (no. cv522). . the number of ic packages enclosed in the embossed carrier tape per reel shall, in principle. be as listed below. package type number of ic packages/reel sop14-p-225 2,500 pcs ___________----____---------- _________.___________________-------------------------------------- sop16-p-225 2,500 pcs ____________________________ __________.___________________-------------------------------------- sop24-p-450 1.500 pcs ______________________________________.-______________---_---------------------- ---___-_--____-- sop28-p-450 1,000 pcs ______________________________________.___________________-------------------------------------- sop32-p-525 1,000 pcs ______________________________________._______________---_-------------------------------------- sop44-p-600 750 pcs __________-----____---------- _________.______________________________--------------------------- tsop$o-p-0813. 1,000 pcs 4 - 8. indications *the following shall be indicated on the taping reel and the packing case. l)part numger (product name) 2)storage quantity 3)production date 4)manufacture?s name (sharp) 4-9. protection while in transit embossed carrier tape should be free from deformed ic leads and deterioration in electrical characteristics. 5. packing specification (dry packing for surface mount packages) dry packing is used for the purpose of maintaining ic quality after mounting packages on the pcb (printed circuit board). when the epoxy resin which is used for plastic packages is stored at high humidity, it may absorb 0.15% or more of its weight in moisture. if the surface mount type package for a relatively large chip absorbs a large amount of moisture between the epoxy resin and insert material (e.g. chip, lead frame) this moisture may suddenly vaporize into steam when the entire package is heated during the soldering process (e.g. vps). this causes expansion and results in separation between the resin and insert material, and sometimes cracking of the package. this dry packing is designed to prevent the above problem from occurring in surface mount packages. please conform to the following conditions concerning the storage and opening of dry packing. sharp lrs13023 54 5- 1. store under conditions shown below before opening the dry packing (1) temperature range : 5-40x (2) humidity : 80% rh or less 5-2. notes on opening the dry packing before opening the dry packing, prepare a working table which is grounded against esd and use a grounding strap. 5-3. storage after opening the dry packing perform the following to prevent absorption of moisture after opening, ( 1) after opening the dry packing, store the ics in an environment with a temperature of 5--25c and a relative humidity of 60% or less and mount ics within 3 days after opening dry packing. (2) to re-store the ics for an extended period of time within 3 days after opening the dry packing, use a dry box or re-seal the ics in the dry packing with desiccant (whoes indicater is blue), and store in an environment with a temperature of 5-40c and a relative humidity of 80% or less, and mount ics within 2 weeks. (3) total period of storage after first opening and re-opening is within 3 days, and store the ics in the same environment as sect ion 5-3. (1). first opening+ x1 +re-sealing+ y +re-opening- xz -mount ing - ics in dry ! 5--25x i 5 -40c 5~25c packing i 60%rh or less i 8o%rh or less j 60%rh or less ( 5 - 4. baking (drying) before mounting ( 1) baking is necessary (a) if the humidity indicator in the desiccant (b) if the procedure in section 5-3 could not ( 2) recommended baking conditions if the above conditions (a) and (b) are applicab becomes pink be per formed le, bake it be mounting. the recommended conditions are 16-24 hours at 120c hours at 150c. note that the embossed carrier tape can not be fore or 5-10 baked at the above temperature. please transfar ics to heat resistant carrier. (3) storage after baking after baking ics, store the ics in the same environment as section 5-3.(l). sharf= lrs13023 55 lrs1302 i yyww xxx c -i 12. 4*0.3 z -i\ -i detail a \ 01 see detail a me i tsop40-p-0813/0.4 lead finish! plating note plastic body dimensions do not include q&e ; burr of resin. rawing no. i aa2017 unit ?i mm sharp lrs13023 56 emboss taping type i 1 ic taping dlrectlon 1 the drawing direction of tape - [leader side md !3d side of taf'e ] adhe$ig ;;;e(?aper) . filled emboss(with ic package) i carrier tape ; : 500mm min. 1 *- --_-. i hf j bit* lame i emboss taping type ncve 4-m j drawing no. i cv522 unit i mm sharp lrs13023 57 ir j fr#i% me i ec28-0813tspts note ye / @awing no. j cv674 unit 1 mm sharp lrs13023 ame i reel for emboss carrier taping note drawing no. j cv755 ll?z j unit j mm sharp lrs13023 case size : 345x345x55 (mm> %rj external appearance of packing #if% name i case for emboss carrier taping note ( 4w f drawing no. 1 bj279 ) unit i mm 1 |
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